S. Lee, J. Lee, H. Lee and S. Kang, "VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2025.3593691.

J. Joung, S. Lee, J. Park, J. Kim, L. Jung and S. Kang, "CLAPS: A Graph Clustering Based Approach for Partial Scan Design," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2025.3576314.

D. Han, D. Won, S. Kim and S. Kang, "TSV Built-In Self-Repair Architecture for Lifespan Reliability Enhancement of HBM," in IEEE Transactions on Reliability, doi: 10.1109/TR.2024.3434631.

H. Lee, J. Lee and S. Kang, "An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 5, pp. 1452-1456, May 2025, doi: 10.1109/TVLSI.2024.3504539.

J. Lee, H. Lee, S. Lee and S. Kang, "A New ISA for High-Speed and Area-Efficient ALPG," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 7, pp. 3358-3362, July 2024, doi: 10.1109/TCSII.2024.3364057.

Purely self-rectifying memristor-based passive crossbar array for artificial neural network accelerators

Self-rectifying resistive memory in passive crossbar arrays

In-doped GeSbSeTe thin films for increased memory window of selector-only-memory devices

Optimized chalcogenide medium for inherently activated resistive switching device

GeSSeTe-based selector-only-memory via unipolar operation

Beyond Page Migration: Enhancing Tiered Memory Performance via Integrated Last-Level Cache Management and Page Migration, IEEE/ACM International Symposium on Microarchitecture (MICRO), 2025

EcoCore: Dynamic Core Management for Improving Energy Efficiency in Latency-Critical Applications, IEEE/ACM International Symposium on Microarchitecture (MICRO), 2025

BrokenSleep: Remote Power Timing Attack Exploiting Processor Idle States, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025

vSPACE: Supporting Parallel Network Packet Processing in Virtualized Environments through Dynamic Core Management, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2024

GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State, IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021

An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation-2022 IEEE Journal of Solid-State Circuits (JSSC)

21.1 A 1.125Gb/s 28mW 2m-Radio-Range IR-UWB CMOS Transceiver-2021 IEEE International Solid-State Circuits Conference (ISSCC)

A Time Domain Artificial Intelligence Radar System Using 33-GHz Direct Sampling for Hand Gesture Recognition-2020 IEEE Journal of Solid-State Circuits (JSSC)

A Time Domain Artificial Intelligence Radar for Hand Gesture Recognition Using 33-GHz Direct Sampling-2019 Symposium on VLSI Circuits

An IR-UWB CMOS Transceiver for High-Data-Rate, Low-Power, and Short-Range Communication-2019 IEEE Journal of Solid-State Circuits (JSSC)

HALO: Loop-aware Bootstrapping Management for Fully Homomorphic Encryption (ASPLOS 2025)

Performance-aware Scale Analysis with Reserve for Homomorphic Encryption (ASPLOS 2024)

Occamy: Memory-efficient GPU Compiler for DNN Inference (DAC 2023)

Decoupling Schedule, Topology Layout, and Algorithm to Easily Enlarge the Tuning Space of GPU Graph Processing (PACT 2022)

HECATE: Performance-Aware Scale Optimization for Homomorphic Encryption Compiler (CGO 2022)

"BitL: Hybrid Bit-Serial and Parallel Processing for Critical Path Reduction", 2025 58th IEEE/ACM International Symposium on Microarchitecture (MICRO)

"WINS: Winograd Structured Pruning for Fast Winograd Convolution", 2025 IEEE/CVF International Conference on Computer Vision (ICCV)

"Ditto: Accelerating Diffusion Model via Temporal Value Similarity", 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA)

"Garibaldi: A Pairwise Instruction-Data Management Scheme for Enhancing Shared Last-Level Cache Performance in Server Workloads", 2025 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA)

"DEPrune: Depth-wise Separable Convolution Pruning for Maximizing GPU Parallelism", 2024 38th Annual Conference on Neural Information Processing Systems (NeurIPS)

H. -S. Lee, J. Myeong and B. -W. Min, "A 26GHz CMOS 3× Subharmonic Mixer With a Fundamental Frequency Rejection Technique," in IEEE Access, vol. 8, pp. 122986-122996, 2020

B. Suh and B. -W. Min, "A 28-GHz Reconfigurable SP4T Switch Network for a Switched Beam System in 65-nm CMOS," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 6, pp. 2057-2064, June 2020

M. Jung and B. -W. Min, "A Compact 3–30-GHz 68.5-ps CMOS True-Time Delay for Wideband Phased Array Systems," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12, pp. 5371-5380, Dec. 2020

K. Park, J. Myeong, G. M. Rebeiz and B. -W. Min, "A 28-GHz Full-Duplex Phased Array Front-End Using Two Cross-Polarized Arrays and a Canceller," in IEEE Transactions on Microwave Theory and Techniques, vol. 69, no. 1, pp. 1127-1135, Jan. 2021

K. Park and B. -W. Min, "Delay-Sum Group Delay Controller With Low-Loss and Low-Phase Variation," in IEEE Transactions on Microwave Theory and Techniques, vol. 69, no. 1, pp. 825-832, Jan. 2021

S. Kang, S. Lee, Y.-W. Kim, J. Kim, H.-J. Shin, H. Ju, K. Lee, and K. Park*, "A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference," IEEE Journal of Solid-State Circuits (JSSC, 2025)

K. Park, M. Shim, H.-G. Ko, B. Nikolić, and D.-K. Jeong, “Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector,” IEEE Journal of Solid-State Circuits (JSSC, 2022)

D. Kang, J.-S. Park, Y.-W. Kim, S. Lee, K. Kim, H.-G. Ko, and K. Park*, "An 18-Tb/s/mm PAM-3 On-Chip Link with Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)

S. Lee, D. Yun, J. Kim, S. Kang, Y.-W. Kim, K. Lee, H. Ju, S. Lee, and K. Park*, "A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)

Y. Jung, Y. -W. Kim, S. Lee, S. Kang, and K. Park*, "A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver with Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)

IEEE Electron Device Letters, “Analysis of the role of interfacial layer in ferroelectric FET failure as a memory cell”, 2024, IF: 4.1

Nanoscale, “Exploration of structural influences on the ferroelectric switching characteristics of ferroelectric thin-film transistors”, 2024, IF: 5.8

Advanced Electronic Materials, "Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training", 2024, IF: 5.3

IEEE Electron Device Letters, “Demonstration of Pulse Width Modulation Function Using Single Positive Feedback Device for Neuron”, 2022, IF: 4.1

Nanoscale, "Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy", 2022, IF: 5.8

Y. Kim and W. Song, “Genie Cache: Non-blocking Miss Handling and Replacement in Page-Table-based DRAM Cache,” IEEE/ACM International Symposium on Microarchitecture (MICRO), Nov. 2024, pp. 983-996.

Y. Kim, H. Kim, and W. Song, “NOMAD: Enabling Non-blocking OS-Managed DRAM Cache via Tag-Data Decoupling,” IEEE International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2023, pp. 193-205.

H. Kim, S. Ahn, Y. Oh, B. Kim, W. Ro, and W. Song, “Duplo: Lifting Redundant Memory Accesses of Deep Neural Networks for GPU Tensor Cores,” IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct. 2020, pp. 725-737.

H. Choi, C. Park, E. Kim, and W. Song, “Nona: Accurate Power Prediction Model Using Neural Networks,” ACM/IEEE Design Automation Conference (DAC), no. 38, June 2024, pp. 1-6.

T. Lim, H. Kim, J. Park, B. Kim, and W. Song, “RoTA: Rotational Torus Accelerator for Wear Leveling of Neural Processing Elements,” Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar. 2025.

J.-W. Jang, J. Oh, Y. Kong, J.-Y. Hong, S.-H. Cho, J. Lee, H. Yang, and J.-S. Yang, "Accelerating Retrieval Augmented Language Model via PIM and PNM Integration", IEEE/ACM International Symposium on Microarchitecture (MICRO), 2025

H. Lee and J.-S. Yang, "Self-Error Detection and Correction Techniques for Reliable and Efficient Selector-Only Memory", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

I. Choi, and J.-S. Yang, "DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks", ACM/IEEE Design Automation Conference (DAC), 2025 

I. Choi, Y.-S. Yoon and  J.-S. Yang, "Bit-slice Architecture for DNN Acceleration with Slice-level Sparsity Enhancement and Exploitation", IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025 

D.-J. Shin, I. Choi, and J.-S. Yang, "ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm", ACM/IEEE Design Automation Conference (DAC), 2024

TFET-Based Pixel Source Follower of CMOS Image Sensor for Improved Linearity and High Signal-to-Noise Ratio, IEEE Sensors Journal, 2023

Methodology for Plasma Diagnosis and Accurate Virtual Measurement Modeling Using Optical Emission Spectroscopy, IEEE Sensors Journal, 2019

Real-Time Plasma Uniformity Monitoring via Selective Plasma Light Intensity Measurement Using Transparent-LCD-Module-Adapted Optical Emission Spectroscopy, IEEE Sensors Journal, 2021

2-D Quantum Confined Threshold Voltage Shift Model for Asymmetric Short-Channel Junctionless Quadruple-Gate FETs, IEEE Transactions on Electron Devices, 2021

Junction Engineering-Based Modeling and Optimization of Deep Junction Silicon Single-Photon Avalanche Diodes for Device Scaling, IEEE Transactions on Electron Devices, 2022

Jeong, H., Kim, S., Jung, J., Lee, K.J., "A 30.7 TOPS/W Sparsity-Aware Analog-Digital Hybrid eDRAM CIM by Effective Row Activation with Simultaneous Multi-Row-Multi-Task Control", IEEE European Solid-State Electronics Research Conference, Sep. 2025

Seo, B., Jung, J., Han, D., Lee, K.J., "A LiDAR-PNN Pipelined Processor with Cylindrical Bin Partitioning and Halo Indexing for 3D Perception in Outdoor Autonomous Driving Applications", IEEE Journal of Solid-State Circuits, Jun. 2025

Jeong, H., Kim, S., Shin, J., Park, K., Lee, K.J., "A 273.48 TOPS/W and 1.58 Mb/mm2 Analog-Digital Hybrid CIM Processor with Transpose Ternary-eDRAM Bitcell", IEEE Asian Solid-State Circuits Conference, Nov. 2024

Jung, J., Kim, S., Seo, B., Jang, W., Lee, S., Shin, J., Han, D., Lee, K.J., "LSPU: A Fully-Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-Network Segmentation and Multi-level kNN Acceleration", IEEE International Solid-State Circuits Conference, Feb. 2024

Lee, K., Bong, K., Kim, C., Jang, J., Kim, H., Lee, J., Lee, K., Kim, G., Yoo, H., "A 502GOPS and 0.984mW Dual-mode ADAS SoC with RNN-FIS Engine for Intention Prediction in Automotive Black Box System", IEEE International Solid-State Circuits Conference, Feb. 2016

D. H. Lee, S. W. Kang, L. F. Register, S. K. Banerjee, J. Chang*, “Efficient and Accurate Full Band Semi-Classical Monte-Carlo Transport Simulation Using Smearing Method and Marching Tetrahedra Algorithm”, SISPAD, Sep 24-26, 2025, Grenoble, France.

S. Youn, D. H. Lee, J. Chang*, “Full Band Semi-Classical Monte-Carlo Simulation of Layer Number-Dependent Electron Transport in MoS2 and InSe”, SISPAD, Sep 24-26, 2025, Grenoble, France.

D. H. Lee, S. R. Das, J. Kwon*, J. Chang*, “FDSOI-Based Reconfigurable FETs: A Ferroelectric Approach”, IEEE Transactions on Nanotechnology, vol. 24, pp. 277-281 (2025).

C. Lee=, D. Kim=, E. Yang, J. Ma, K. Kang*, J. Chang*, “Electrically Binary and Ternary Convertible CMOS Inverter and Logic Gate Using Complementary Field-Effect Transistors Based on Vertically Stacked MoS2/WSe2 n-/p- Field-Effect Transistors”, Advanced Functional Materials(2025).

J. E. Seo=, M. Gyeon=, J. Seok, S. Youn, T. Das, S. Kwon, T. S. Kim, D. K. Lee, J. Y. Kwak*, K. Kang*, J. Chang*, “Improvement of Contact Resistance and Three-Dimensional Integration of Two-Dimensional Material Field-Effect Transistors Using Semi-metallic PtSe2 Contacts”, Advanced Functional Materials, 2407382 (2024).

S. Kim, G. Kim, K. Baek, K. Cho, H. Kim, Y. Jung, D. Seo, S. Baeck, S. Lee, and S.-O. Jung “A High-Density Low-Leakage and Low-Power Fully-Voltage-Stacked SRAM for IoT Application", IEEE Journal of Solid State Circuits.

D. Lim, S. Lim, D. Ko, I. Jung, G. Kim, D. Kim, D. Ha, S. Park, H. Chae, S. Yei, T. Na, and S.-O. Jung “A 3X Offset, 2.9X Power, 1.3X Sensing Time, and 4X Area Reduction Direct Input Transfer Offset Cancel DRAM IO Sense Amplifier with Static Current-Free Pre-Sensing", IEEE Journal of Solid State Circuits.

J. Kang, K. Cho, S. Kim, G. Kim,H. Kim, H. Kim, D. Seo, S. Baeck, S. Yoon, and S.-O. Jung “A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage with Minimal Power Overhead ", IEEE Journal of Solid State Circuits.

S. H. Lim, I. Jung, G. S. Kim, D. H. Ko and S.-O. Jung "Dual-input Stacked Inverter-based Single-ended DRAM Sense Amplifier Using BL Switches for Low power High-speed Sensing ", IEEE Journal of Solid State Circuits.

T. Kim, J. Y. Kim, J. You, H. Chae, B. Moon, K. Sohn and S.-O. Jung “A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15Gb/s for TSV Interface", IEEE Journal of Solid State Circuits.

Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Yung-Hsiang Lu and Giovanni De Micheli, "Dynamic Power Management for Nonstationary Service Requests," IEEE Transactions on Computers, vol. 51, no. 11, pp. 1345-1361, Nov. 2002

Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabrio Luculli and Marco Carilli, "Value-sensitive Automatic Code Specialization for Embedded Software," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1051-1067, Sep. 2002

Eui-Young Chung, Giovanni De Micheli, Marco Carilli, Luca Benini and Gabriele Luculli, "Value-based Source Code Specialization for Energy Reduction," ST Journal of System Research, vol. 3, no. 1, pp. 29-48, Apr. 2002

Byoung Jin Kim, Taeyang Jeong, SeongJun Yun and Eui-Young Chung, "DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Early Access

Taeyang Jeong and Eui-Young Chung, "PipePIM: Maximizing Computing Unit Utilization in ML-Oriented Digital PIM by Pipelining and Dual Buffering," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, pp. 4585-4598, Dec. 2024

UPP: Universal Predicate Pushdown to Smart Storage

Reconstructing Out-of-Order Issue Queue

CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices

Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction

Kashif Inayat, Inayat Ullah and Jaeyong Chung, "Factored Systolic Arrays based on Radix-8 Multiplication for Machine Learning Acceleration", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol 32, No. 7, July 2024 (TVLSI Spotlight Article) 

Phouc Pham and Jaeyong Chung, "AGD: A Learning-based Optimzation Framework for EDA and its Application to Gate Sizing", IEEE/ACM Proc. Design Automation Conference (DAC), July 2023 

Kashif Inayat and Jaeyong Chung, "Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, 2022 

Phuoc Pham, Jacob A. Abraham, and Jaeyong Chung, "Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer", IEEE Access, Vol. 9, March 2021 (code)

Kashif Inayat, Fahad Bin Muslim, Tayyeb Mahmood, and Jaeyong Chung, "FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach", Journal of Systems Architecture, 2024

Dongho. Kim, S. Kim, J. Lee, H. Kim, S. Lee, J. Park and H. Jeong, “Bayesian learning-driven Memory Design with Automated Circuit Variant Generation,” IEEE Transactions on Computer-Aided of Integrated Circuits and Systems (IEEE TCAD), Jan.2025.

Seokhun Kim, Junseo Lee, Dongho Kim, Jihwan Park, Sangheon Lee, and Hanwool Jeong, "Simultaneous Optimization of Various-Sized SRAM Instances through Machine Learning-Driven Transistor Sizing and Leafcell Circuit Pool Construction," IEEE Transactions on Circuits and Systems (IEEE TCAS-1), Jan.2025.

T. Yoon, H. Jeong, "Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 8, pp. 2618-2630, Aug. 2023, 

Jaehyun Park, Sangheon Lee, Hanwool Jeong, "Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM" IEEE Transactions on Circuits and Systems-1, vol. 70, no. 2, pp. 797-805, Feb. 2023

Junseo Lee, Jihwan Park, Seokhun Kim and Hanwool Jeong “Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization”, IEEE Transactions on Circuits and Systems-1, Sept. 2023

A 0.5ms 47.5nJ Resistor-to-Digital Converter for Resistive BTEX sensor Achieving 0.1-to-5 ppb Resolution

A 65 dB-SNDR Pipelined SAR ADC using PVT-Robust Capacitively-Degenerated Dynamic Amplifier

A 113.3 dB Dynamic Range 600 frames/s SPAD X-ray Detector with Seamless Global Shutter and Time-Encoded Extrapolation Counter

A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC with Pulse-Width Modulation Frontend

An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth

Kyung-Sik Choi†, Basem Abdelaziz Abdelmagid†, Yuqi Liu, and Hua Wang, “A D-Band Concurrent 20-Beam MIMO Transmitter Array with A Four-Element Joint Static/Dynamic Beam-Multiplication Beamformer,” in IEEE Journal of Solid-State Circuits (Accepted).

Kyung-Sik Choi†, Hokeun Lee†, Byeonghun Yun, and Sang-Gug Lee, “A D-band Low-Noise and High-Gain Receiver Front-End Adopting Gmax-Driven Active Mixer,” in IEEE Transactions on Microwave Theory and Techniques(Accepted). (†Co-first author)

Kyung-Sik Choi, Keun-Mok Kim, Jinho Ko, and Sang-Gug Lee, “A 915 MHz Transmitter with 210 μW ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer,” in IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3336-3347, Nov. 2022, doi: 10.1109/JSSC.2022.3172467

Kyung-Sik Choi, Keun-Mok Kim, Dzuhri Radityo Utomo, In-Young Lee, and Sang-Gug Lee, “A Fully-Integrated 490 GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL," in IEEE Journal of Solid-State Circuits, vol. 57, no. 9, pp. 2626-2639, Sept. 2022, doi: 10.1109/JSSC.2022.3159656

Kyung-Sik Choi, Jinho Ko, Keun-Mok Kim, Jusung Kim, and Sang-Gug Lee, “A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA,” in IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 892-905, March 2022, doi: 10.1109/JSSC.2021.3096945

An 80-Gb/s/pin single-ended voltage-mode PAM-4 transmitter with a pulsewidth pre-emphasis and a 4-tap FFE in 28-nm CMOS JK Park, DW Rho, SJ Yang, WY Choi IEEE Journal of Solid-State Circuits, 2024

Novel monolithic all-silicon coherent transceiver sub-assembly based on ring modulators Y Jo, M Oberon, A Peczek, Y Ji, M Kim, HK Kim, MH Kim, PM Seiler, ...Journal of Lightwave Technology 42 (20), 7298-7306, 2024

A 4-λ× 28-gb/s/λ silicon ring-resonator-based wdm receiver with a reconfigurable temperature controller HK Kim, JH Lee, M Kim, Y Jo, S Lischke, C Mai, L Zimmermann, WY Choi Journal of Lightwave Technology 42 (7), 2296-2302, 2023

A 20 Gb/s CMOS single-chip 850 nm optical receiver SJ Yang, JH Lee, MJ Lee, WY Choi Journal of Lightwave Technology 42 (13), 4525-4530, 2024

A Large-Signal SPICE Model for VCSEL Based on Piece-wise Linear RLC Elements K Kim, JS Kim, JY Kim, WY Choi IEEE Photonics Technology Letters, 2024

Scheduling Weight Transitions for Quantization-Aware Training (International Conference on Computer Vision 2025)

Toward INT4 Fixed-Point Training via Exploring Quantization Error for Gradients (European Conference on Computer Vision 2024)

Instance-Aware Quantization for Vision Transformers (Conference on Computer Vision and Pattern Recognition 2024)

Distance-aware Quantization (International Conference on Computer Vision 2021)

Network Quantization with Element-wise Gradient Scaling (Conference on Computer Vision and Pattern Recognition 2021)

IEEE Journal of Solid-State Circuits, “A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3”, 2024

IEEE Solid-State Circuits Letters, “An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing”, 2024

IEEE Journal of Solid-State Circuits, “A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ”, 2023

IEEE Transactions on Circuits and Systems II: Express Briefs, “A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend”, 2023

IEEE Transactions on Components, Packaging and Manufacturing Technology, “Novel Optimization Methodology of Design Parameters in High-Speed Differential Via for PCIe Gen5 Channels Based on Particle Swarm Optimization Algorithm”, 2023

IEEE Journal of Solid-State Circuits, “A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3”, 2024

IEEE Solid-State Circuits Letters, “An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing”, 2024

IEEE Journal of Solid-State Circuits, “A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ”, 2023

IEEE Transactions on Circuits and Systems II: Express Briefs, “A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend”, 2023

IEEE Transactions on Components, Packaging and Manufacturing Technology, “Novel Optimization Methodology of Design Parameters in High-Speed Differential Via for PCIe Gen5 Channels Based on Particle Swarm Optimization Algorithm”, 2023

IEEE International Solid-State Circuits Conference, "A 0.64μm 4-Photodiode 1.28μm 50Mpixel CMOS Image Sensor with 0.98e- Temporal Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower", 2023

IEEE Symposium on VLSI Technology and Circuits, "An Indirect Time-of-Flight CMOS Image Sensor Achieving Sub-ms Motion Lagging and 60fps Depth Image from On-chip ISP", 2023

International Electron Devices Meeting, "Optical design of dispersive metasurface nano-prism structure for high sensitivity CMOS image sensor", 2023

IEEE Symposium on VLSI Technology and Circuits, "A 0.6 ㎛ Small Pixel for High Resolution CMOS Image Sensor with Full Well Capacity of 10,000e- by Dual Vertical Transfer Gate Technology", 2022

International Electron Devices Meeting, "A 140 dB Single-Exposure Dynamic-Range CMOS Image Sensor with In-Pixel DRAM Capacitor", 2022

Nature Communication, “Interplay between electrochemical reactions and mechanical responses insilicon-graphite anodes and its impact on degradation, 2021, IF 17.69

Nature Energy, “High-energy long-cycling all-solid-state lithium metal batteries enabled by silver-carbon composite anode”, 2020, IF:

IEEE International conference on Electronics, Circuits and Systems, “DVFS method of memory hierarchy based on CPU microarchitectural information”, 2022, IF:

IEEE Vehicular Technology Conference, “An adaptive and Rotated Transmission for Physical layer Security”, 2022, IF:

IEEE International Conference on Consumer Electronics, “A new DVFS algorithm to minimize energy consumption on system-on-chip architecture and electrical characteristics”, 2022, IF:

IEEE Vehicular Technology Conference, “ An Enhanced Cell Reselection Scheme for Dual SIM Dual Standby User Equipment in 5G networks”, 2021, IF:

IEEE Vehicular Technology Conference, The Reinforcement Learning based Interference Whitening Scheme for 5G“, 2021, IF: